MAKE.EXE
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MAKE.EXE is a command-line utility that helps you manage project compilation and link cycles. MAKE is not inherently tied to compiling and linking, but is a more generic tool for executing commands based on file dependencies. MAKE helps you quickly build projects by compiling only the files you have modified since the last compilation. In addition, you can set up rules that specify how MAKE should deal with the special circumstances in your builds.
Contents
MAKE Basics
MAKE uses rules you write along with its default settings to determine how it should compile the files in your project. For example, you can specify when to build your projects with debug information and to compile your .OBJ files only if the date/time stamps of a source file are more recent than the .OBJ itself. If you need to force the compilation of a module, use TOUCH.EXE to modify the time stamp of one of the module's dependents.
In an ASCII makefile, you write explicit and implicit rules to tell MAKE how to treat the files in your project; MAKE determines whether it should execute a command on a file or set of files using the rules you set up. Although your commands usually tell MAKE to compile or link a set of files, you can specify nearly any operating system command with MAKE.
Command-Line Syntax
MAKE [<options>...] [<target>[<target>]]
You must separate the MAKE command from the options and target arguments with spaces.
When specifying targets, you can use wildcard characters (such as * and ?) to indicate multiple files.
Command-Line Elements
| Element | Description |
|---|---|
<options> |
MAKE options that control how MAKE works. See "Make Command Options" in this topic. |
<target> |
The name of the target listed in the makefile that you want to build. |
To display the command-line help, enter:
make -?
or:
make -h
Command-Line Options
You can use command-line options to control the behavior of MAKE. MAKE options are case-sensitive and must be preceded with either a hyphen - or slash /.
You must separate the MAKE command from the options and target arguments with spaces. When specifying targets, you can use wildcard characters (such as * and ?) to indicate multiple files.
Many of the command-line options have equivalent directives that you can use within the makefile.
MAKE.EXE supports the command-line options listed in the following table:
MAKE Command-Line Options
| Option | Description |
|---|---|
|
|
Shows the command-line help for the MAKE options. Default settings are shown with a trailing plus sign. |
-a |
Checks dependencies of include files and nested include files associated with .OBJ files and updates the .OBJ if the .h file changed. See also |
-B |
Builds all targets regardless of file dates. |
-c |
Caches autodependency information, which can improve MAKE speed. Use with |
-D<macro> |
Defines macro as a single character, causing an expression |
[-D]<macro>=[<string>] |
Defines |
-d<directory> |
Specifies the drive and the directory that MAKER (the real mode version of MAKE) uses when it swaps out of memory. This option must be used with |
-e |
Ignores a macro if its name is the same as an environment variable. MAKE uses the environment variable instead of the macro. |
-f<filename> |
Uses |
-I<directory> |
Searches for include files in the current directory first, then in the specified directory. |
-i |
Ignores the exit status of all programs run from the makefile and continues the build process. |
-K |
Keeps temporary files that MAKE creates (MAKE typically deletes temporary files). |
-m |
Displays the date and timestamp of each file as MAKE processes it. |
-n |
Prints the MAKE commands but does not perform them. This is helpful for debugging makefiles. |
-N |
Causes MAKE to mimic Microsoft's NMAKE. |
-p |
Displays all macro definitions and implicit rules before executing the makefile. |
-q |
Returns 0 if the target is up-to-date and nonzero if it is not up-to-date (for use with batch files). |
-r |
Ignores any rules defined in BUILTINS.MAK. (See BUILTINS.MAK in this topic.) |
-s |
Suppresses onscreen command display (silent). |
-S |
Swaps MAKER out of memory while commands are executed, reducing memory overhead and allowing compilation of large modules. MAKE ignores this option. |
-U<macro> |
Undefines the previous macro definition of |
-W<filename> |
Writes MAKE into the |
For example, to use a file called PROJECTA.MAK as the makefile, type:
MAKE -fPROJECTA.MAK
Default MAKE Actions
When you issue a MAKE command, MAKE looks for the file BUILTINS.MAK, a file that you create to contain the default rules for MAKE (use the -r option to ignore the default rules). MAKE looks for this file first in the current directory, then in the directory where MAKE.EXE is stored. After loading BUILTINS.MAK, MAKE looks in the current directory for a file called MAKEFILE or MAKEFILE.MAK (use the -f option to specify a file other than MAKEFILE). If MAKE cannot find the makefile, it generates an error message.
After loading the makefile, MAKE tries to build only the first explicit target listed in the makefile by checking the time and date of the dependent files of the first target. If the dependent files are more recent than the target file, MAKE executes the commands to update the target.
If one of the first target's dependent files is used as a target elsewhere in the makefile, MAKE checks that target's dependencies and builds it before building the first target. This chain reaction is called a linked dependency.
If something during the build process fails, MAKE deletes the target file it was building. Use the .precious directive if you want MAKE to keep the target when a build fails.
You can stop MAKE after issuing the MAKE command by pressing CTRL+Break or CTRL+C.
About makefiles
A makefile is an ASCII file that contains the set of instructions that MAKE uses to build a certain project. Although MAKE assumes your makefile is called MAKEFILE or MAKEFILE.MAK, you can specify a different makefile name with the -f option.
MAKE either builds the targets you specify with the make command or it builds the first target it finds in the makefile. To build more than a single target, use a symbolic target in your makefile.
Makefiles can contain:
- Comments (precede a comment with a number sign
#) - Explicit and implicit rules
- Macros
- Directives
Symbolic Targets
A symbolic target forces MAKE to build multiple targets in a makefile. When you specify a symbolic target, the dependency line lists all the targets you want to build (a symbolic target basically uses linked dependencies to build more than one target). (See "linked dependencies" in the Default MAKE Actions section in this topic.)
For example, the following makefile uses the symbolic target AllFiles to build both FILE1.EXE and FILE2.EXE:
AllFiles: file1.exe file2.exe #Note that AllFiles has no commands file1.exe: file1.obj bcc32 file1.obj file2.exe: file2.obj bcc32 file2.obj
Rules for symbolic targets
Observe the following rules when you use symbolic targets:
- Do not type a line of commands after the symbolic target line.
- A symbolic target must have a unique name; it cannot be the name of a file in your current directory.
- Symbolic target names must follow the operating system rules for naming files.
BUILTINS.MAK
You can create the optional file BUILTINS.MAK and store in it the standard rules and macros that you want MAKE to use when it builds the targets in a makefile. To ignore this file when it exists, use the -r MAKE option.
Here is a sample of a BUILTINS.MAK file:
# # C++Builder BUILTINS.MAK #
CC = bcc32 RC = brcc32 AS = tasm32
.asm.obj:
$(AS) $(AFLAGS) $&.asm
.c.exe:
$(CC) $(CFLAGS) $&.c
.c.obj:
$(CC) $(CFLAGS) /c $&.c
.cpp.exe:
$(CC) $(CFLAGS) $&.cpp
.cpp.obj:
$(CC) $(CPPFLAGS) /c $&.cpp
.rc.res:
$(RC) $(RFLAGS) /r $&
.SUFFIXES: .exe .obj .asm .c .res .rc
!if !$d(BCEXAMPLEDIR) BCEXAMPLEDIR = $(MAKEDIR)\..\EXAMPLES
!endif