Built-In Assembler support for AVX2 and AVX-512
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Built-In Assembler modules (CHASM and CHASM64) linked in the Olympus Delphi compiler for Win32 and Win64 support AVX2 and AVX-512 instructions.
Attention: You’d need an AVX-512 compatible CPU (like one of the recent INTEL CPUs) to test this feature. You can find more information at:
https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#CPUs_with_AVX-512
Contents
New Registers
| Registers | dcc32 | dcc64 |
|---|---|---|
| XMM16 .. XMM31 |  | |
| YMM0 .. YMM7 | |
|
| YMM8 .. YMM31 | | |
| ZMM0 .. ZMM7 | |
|
| ZMM8 .. ZMM31 | | |
| BND0 .. BND3 | |
|
| K0 .. K7 | |
|
New Instruction Prefixes
| Instruction Prefix | dcc32 | dcc64 | Intel Syntax |
|---|---|---|---|
| xacquire | |
|
|
| xrelease | |
|
|
| <evex> | |
|
{evex} |
New Expression Prefixes
| Prefix | dcc32 | dcc64 |
|---|---|---|
| oword | |
|
| yword | |
|
| zword | |
|
Difference between Delphi Syntax and Intel Syntax
Unfortunately, Intel AVX-512 syntax uses curly brackets characters { } which is already used as comment begin/end in Delphi.
So, this implementation uses less-than and greater-than characters < > instead.
| Category | Delphi Syntax | Intel Syntax |
|---|---|---|
| Opmask register | <k1> ,, <k7> | {k1} .. {k7} |
| Zeroing modifier | <z> | {z} |
| Embedded broadcast | <1to2> <1to4> <1to8> <1to16> | {1to2} {1to4} {1to8} {1to16} |
| Static rounding-mode | <sae> <rn-sae> <rd-sae> <ru-sae> <rz-sae> | {sae} {rn-sae} {rd-sae} {ru-sae} {rz-sae} |
| Force EVEX encoding prefix | <evex> | {evex} |